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emerging Apps And Challenges For Packaging | JN0-632 practice exam and exam Questions

superior packaging is taking part in a much bigger function and fitting a extra viable option to advance new gadget-degree chip designs, nevertheless it also gifts chipmakers with a difficult array of alternatives and infrequently a hefty rate tag.

automobile, servers, smartphones and different techniques have embraced advanced packaging in a single form or yet another. For other purposes, it’s overkill, and a less complicated commodity package will suffice. still, superior packaging is quick fitting an attractive option for many. The business is constructing new styles of advanced packaging or upgrading the latest technologies for more than a few functions, equivalent to 5G and AI.

It has taken the trade years to get to this element. Assembling dies in a rudimentary kit has been possible for a long time. however as scaling runs out of steam, packaging opens up a whole new set of architectural alternate options that may increase efficiency, in the reduction of power, and add flexibility into designs to each personalize them for specific markets and reduce time to market.

no person package category can meet all needs, however. each software is distinctive, and each has its personal entertaining necessities. In some instances, advanced packaging might also no longer even be the correct solution.

Semiconductor Engineering examined the advantages and challenges of advanced packaging in four markets — servers, networking gadget, sensible glasses and army/aerospace. while here's just a pattern of the feasible applications, it highlights some of the leading concerns and challenges in packaging that chipmakers will face sooner or later.

the whole IC packaging market changed into worth $sixty eight billion in 2019, in keeping with Yole Développement. Of that, the advanced packaging business become $29 billion in 2019 and is expected to grow by means of 6.6% to reach $forty two billion in 2025, in keeping with Yole.

ServersTypically, to boost a leading-edge design, machine makers count on chip scaling. The goal is to pack more functions on a monolithic die at each new method node, with a new node rolling out roughly each 18 to 24 months. but scaling is becoming greater intricate and costly at each node, and the fee/efficiency benefits are diminishing. So while scaling will proceed, now not all components in a equipment will scale equally.

“it is in reality about die economics,” spoke of Walter Ng, vice president of enterprise construction at UMC. “At bleeding-edge nodes, wafer costs are astronomical, so few valued clientele and few purposes can manage to pay for to take capabilities of high priced procedure know-how. Even for shoppers that can come up with the money for the charge, a few of their die sizes are working up in opposition t the highest reticle measurement. That, of direction, outcomes in yield challenges, which then further exacerbates the cost issue. shoppers desire a extra optimized technical answer, so they can carry a greater economical company answer. The amount of time it takes to design and assess a big system-on-a-chip (SoC) at the bleeding part is additionally a priority for a lot of from a time-to-market standpoint.”

within the server world, this facets to each disaggregation — offloading features that do not require or benefit from essentially the most superior digital common sense — in addition to heterogeneous integration using a excessive-pace die-to-die interconnect. There are a couple of alternatives purchasable, but the existing buzz is round chiplets.

In chiplets, a chipmaker may also have a menu of modular dies, or chiplets, in a library, no longer all of which must be developed on the same procedure node. commonly, a design that contains chiplets resembles a monolithic SoC, nonetheless it charges less to boost.

This all sounds good on paper, however there are some challenges. “here is an emerging environment. It’s a brand new model. There are not a lot of specifications when it comes to interfaces. The early adopters of chiplet integration are typically vertically built-in organizations that can control all the design elements, and principally the interfaces,” talked about Eelco Bergman, senior director of business construction at ASE, in a presentation on the fresh IMAPS2020 convention. “nowadays, the chiplet designs should be largely driven by a chip developer, no matter if that’s an IDM or a fabless employer. as the trade evolves and the ecosystems open up, you’ll see this trade.”

Others agreed. “understanding the bus design and interface specs are truly critical. If it’s a proprietary situation, then clearly the customer is going to become taking a lead role there. That should be genuine for some time,” stated Mike Kelly, vice president of advanced package and technology integration at Amkor, in a presentation. “as soon as they set up a place where they have general bus architectures that all and sundry is familiar with and are neatly unique, then design may also be very flexible, even if it’s a vertically integrated enterprise, IDM or an OSAT for that depend.”

AMD, Intel, and a couple of others have delivered chiplet-like architectures. as an instance, as a substitute of a large monolithic die, AMD’s latest server processor line integrates smaller dies in a module, now and again known as a multi-chip module (MCM). The chips are related the usage of a die-to-die interconnect.

referred to as a 2nd chiplet design, AMD’s MCM contains an built-in I/O and reminiscence controller die in response to a 14nm procedure. That die is based in the center. Eight 7nm processor dies are also incorporated in the MCM. 4 processor dies are centered on either side of the I/O die.

Fig. 1: AMD’s EPYC server method with eight core dies and 1 I/O die source: AMD

For its server processor strains, AMD moved to a chiplet-like approach for a number of explanations. “to be able to continue the required performance vogue of 2X efficiency each two years, we’re going to need chiplets to not handiest permit extra transistors at improved yield, but to in the reduction of the entire volume of advanced-node silicon,” pointed out Bryan Black, a senior fellow at AMD, in a presentation.

Going ahead, AMD plans to expand its MCM efforts on the server processor entrance. It additionally plans to boost chiplets the usage of 3D stacking suggestions. “As they move into 3D stacking, we’re going to exacerbate all of those challenges that we’ve been working on in 2d,” Black talked about.

both second- and 3D-primarily based chiplet designs have lots of the same challenges. “Chiplets aren’t free,” Black referred to. “They do have a price linked to them, each in a packaging can charge and an increase in die area can charge. they can’t take a monolithic element with 2X enviornment and divide it into two smaller die that are only 1X enviornment each and every. there is an overhead when communicating between both, in addition to additional power logic, extra coherency good judgment, further clocking controls, and as well as efficient verify controls. they have a ton of extra manage logic in addition to the I/O communique overhead it's required to connect these two dies and make them appear as comparable to being as one die as viable.”

On accurate of that, a package requires dies with decent yields, also referred to as generic first rate die. One bad die in the equipment can result in product or gadget disasters. “there's parametric edition in the entire dies. And so they have a primary examine and characterization problem of multi-die solutions. Some are sluggish. Some are speedy. Some devour more or less vigor,” Black spoke of.

heat, energy distribution, and reliability are also challenges with chiplet-based designs. after which, if the equipment fails, the big question is who takes responsibility. Is it the chip vendor, the IP corporation or the packaging apartment?

For this, the packaging industry can study from past experiences, exceptionally within the early degrees of 2.5D. With 2.5D, dies are stacked or positioned side-by using-facet on suitable of an interposer. The interposer, which contains via silicon vias (TSVs), acts because the bridge between the chips and a board.

within the early tiers of 2.5D, device makers had been wrestling with diverse dies, integration issues and yield challenges. Over time, even though, companies labored in the course of the complications.

“I be aware when the two.5D tasks started,” Amkor’s Kelly referred to. “The number 1 thing that helped us became getting yields up to some extent. Then it wasn’t a big challenge to kind throughout the few yield losses that you had.”

If a die didn’t meet spec, carriers would then conduct an in depth root cause evaluation of the device. This requires a sound trying out approach.

The equal type of recipe can be carried out for heterogenous integration the use of chiplets. As before, constructing dies with good yields is vital. “you will definitely take it to another excessive. You will have more dies and more solder joints. however provided that your fundamental assembly manner is rock strong, it’s no longer going to be as painful of a discussion as they found it with 2.5D,” Kelly talked about.

certainly, the equipment must have respectable yields at proper expenses. however when a failure occurs, it goes again to the corporation. “on the conclusion of the day, the service provider is the one that’s finally liable for the product. but the deliver base that supported that chip business enterprise is there to assist in that failure analysis procedure. once that's recognized, then the liabilities and obligations turn into tons extra clear,” ASE’s Bergman said.

The goal is to prevent screw ups within the first place. That takes a holistic strategy beginning with the design. “in the course of the design phase, they are able to figure out what’s going to work most efficient with the consumer,” mentioned Ken Molitor, chief operating officer at Quik-Pak. “We’ll turnkey the whole undertaking, where they design the substrate, have the substrate fabricated, after which get a hold of a cohesive design. Then, they are able to have it assembled. There are certain milestones (all the way through the manner.) That tends to in the reduction of the possibility on his end and in their end.”

Networking equipmentNetworking device companies face most of the identical challenges. The network is a fancy device that spans from the home office to the cloud. To address these markets, communication device providers sell distinct techniques for numerous ingredients of the community.

for instance, in one a part of the network, Cisco sells a router for colossal-scale service suppliers. A router directs the network using IP statistics packets. Cisco’s latest router is according to its personal, in-condo ASIC. constructed around a 7nm system, Cisco’s monolithic ASIC allows 12.8 Tbps of bandwidth on the equal chip.

Cisco also develops ASICs for its other networking products. different communique machine companies Strengthen ASICs, as smartly.

companies are also exploring or implementing option processes for several explanations. At each node, the ASIC is becoming larger and greater expensive. It additionally accommodates a SerDes (serializer/deserializer), which gives high-pace chip-to-chip communications.

“network bandwidth scaling requirements outcome in an increase in networking ASIC die dimension with each technology technology,” noted Valery Kugel, a senior exotic engineer at Juniper, in a presentation. “(The) SerDes is occupying a big portion of the ASIC enviornment.”

There are other concerns. The ASIC incorporates each digital and analog blocks. The digital portion advantages from scaling, enabling greater features with greater bandwidths. but not every little thing merits from scaling.

“The SerDes function isn't shrinking. this is an analog constitution. It doesn’t scale well,” talked about Nathan Tracy, a technologist and manager of trade standards at TE Connectivity. Tracy is also the president of the Optical Internetworking forum (OIF), an business standards group.

There are a few options right here, together with chiplets. To join dies in a package, OIF is constructing a die-to-die interface normal known as CEI-112G-XSR. XSR connects chiplets and optical engines in MCMs. It allows facts costs up to 112Gbps over a short reach link. XSR continues to be within the draft form.

There are a few easy methods to put in force chiplets and XSR in networking gadget. as an example, the huge ASIC is cut up into two smaller dies, that are connected the usage of an XSR hyperlink.

In a further instance, the significant SerDes block is damaged up into four smaller I/O dies. Then, in an MCM, the ASIC sits in the middle, which is surrounded by way of four smaller I/O chiplets.

Fig. 2: instance of an Ethernet swap SoC requiring die-to-die connectivity. source: Synopsys

additionally, a tool maker could integrate optical engines with a switch chip ASIC in an MCM.

“There’s a lot of industry buzz about co-packaged optics,” Tracy mentioned. “I’m speaking concerning the chance of moving faraway from pluggable optical transceivers at the face blade of the swap to having the optical engine established without delay on the switching silicon. You need a low-energy excessive-pace interconnect. The center of attention of that dialogue is OIF’s XSR construction.”

The adoption of chiplets will rely upon the application. In some circumstances, ASICs nevertheless make experience. There are a few components right here, reminiscent of charge and yield. “It’s all about reducing vigor consumption,” Tracy talked about.

“Use of chiplets permit reducing the main die dimension to healthy within the reticle size limits. however most ICs aren't reticle confined. So this argument simplest works for a extremely small variety of ICs. It’s a powerful argument that doesn’t practice to most designs,” in line with one knowledgeable. “if you split the design in two, you get 2X the number of die per wafer. Assuming the defects ‘D’ per wafer are relatively regular, then your yield goes from X-D to 2X-D. Of direction, it takes twice as many die per equipment, so your beneficial yield is (2X-D)/2 = X-D/2. you have got conveniently reduce the defects in half on the charge of a extra complicated two die versus one die equipment. As multi-die packaging know-how improves over time, this should be much less of a controversy.”

wise glassesThese solutions might also work for networking apparatus, however the client market has distinctive necessities, above all for brand new and rising items.

as an example, in R&D, a few companies are constructing subsequent-generation sensible glasses or AR/VR glasses. digital truth (VR) enables clients to adventure 3D virtual environments. Augmented truth (AR) takes computing device-generated photographs and overlays them on the equipment.

If the technology works, AR/VR glasses may well be used for facts retrieval, face focus, games and language translation. They also might project a presentation or a keyboard on a floor.

“[AR/VR] and their variant gadgets are only in the beginning of their experience to become the subsequent-era computing platform,” observed Chiao Liu, director and research scientist at fb truth Labs, in a paper at last yr’s IEDM.

establishing a valuable and good value pair of sensible glasses isn’t an easy project. These products require new low-power chips, shows and interfaces. In these glasses, the programs are activated the usage of voice, eye gaze, and head/physique movements. All of those applied sciences should be relaxed.

“we are going to want dramatic improvements across the board,” stated Ron Ho, director of silicon engineering at facebook, in a presentation at IMAPS2020. “i want much more performance relative to vigor than i'm able to maintain in systems these days. often, I should run issues quicker with lessen latency.”

To allow wise glasses at the right kind aspect, IC packaging is key. “I need to control packages that enable issues like improved efficiency and reduce latency,” Ho spoke of. “that you can’t force chips to go over a multi-inch trace and burn a bunch of vigour on PCIe. however reasonably you co-package them and put them subsequent to each and every other. and thru TSVs, they have a tons higher bandwidth and higher efficiency connections.”

At IEDM, fb disclosed some clues about its AR/VR glasses, which are in R&D. In a paper, facebook outlined the building of a laptop imaginative and prescient interface technology for AR/VR glasses. The underlying expertise is an superior CMOS picture sensor.

CMOS image sensors provide the digicam services in smartphones and different items. however commonplace graphic sensors aren’t satisfactory for AR/VR glasses. What’s required are machine-perception optimized photograph sensors with advanced packaging. within the paper, facebook described a 3-layer image sensor. the first layer is an image sensor with a processing unit, followed by an aggregation processor, and then a cloud compute platform.

facebook additionally mentioned copper hybrid bonding. For this, the dies are stacked and related the use of a copper-to-copper diffusion bonding method. It’s unclear if facebook will go down this route, however hybrid bonding is a favourite know-how in the graphic sensor world.

armed forces/aerospaceFor a long time, meanwhile, the U.S. branch of defense (DoD) has diagnosed that chip technology is primary for U.S. military superiority. For a considerable number of techniques, the defense neighborhood makes use of chips at each superior and mature nodes. Packaging is also a vital part of the equation.

armed forces/aerospace involves a mess of shoppers with diverse requirements, although there are some average syllabus right here. “We service a lot of distinctive sectors,” Quik-Pak’s Molitor spoke of. “We do service the mil/aero trade. The mil/aero programs are usually lengthy-lived. they're used to coping with components that need to work for 20 to 30 years.”

Mil/aero valued clientele face different challenges. As with the business sector, the can charge of establishing advanced chips is costly, but the benefits are shrinking at each and every node. Plus, the volumes are notably low for the protection group.

every now and then, the defense group uses non-U.S. foundries to achieve advanced chips, however prefers to use onshore providers for safety functions. Mil/aero clients desire a depended on and assured supply chain for both chips and packages.

even so, the DoD is looking for choice methods past chip scaling, namely heterogenous integration and chiplets.

as an instance, Intel turned into recently awarded a new contract for the DoD’s new chiplet effort, called the State-of-the-artwork Heterogeneous Integration Prototype (SHIP) program. beneath the plan, Intel has centered a new U.S. commercial entity round chiplets. This software gives consumers entry to Intel’s packaging capabilities, including the DoD and the defense neighborhood.

There are quite a few materials to the SHIP application. whereas Intel won the digital element of the application, Qorvo was awarded the RF a part of the SHIP assignment. below that mission, Qorvo will installation an RF heterogeneous packaging design, construction and prototyping center in Texas. This center will primarily serve the defense neighborhood.

Qorvo isn’t new to mil/aero. For years, the service provider of RF instruments and different items offers each foundry and packaging functions for mil/aero and the commercial sector. The enterprise develops devices in line with gallium nitride (GaN), gallium arsenide (GaAs) and other tactics.

In mil/aero, the packaging necessities have modified over the years. “when I first began working for Qorvo decades in the past, nobody desired us to ship them packaged elements. Mil/aero desired bare die,” observed Dean White, director of defense and aerospace market approach at Qorvo. “We’ve considered the market change from a armed forces-aerospace type market, which is bare die, to packaging and packaging integration. Packaging is more environmentally mighty than it became years ago. They do lots of packaging for mil/aero in a variety of diverse programs, based upon vigor ranges, heat dissipation and robustness for vibration.”

under the SHIP software, Qorvo will provide heterogenous packaging functions using devices based on GaN, GaAs and silicon. The goal is to satisfy what the DoD calls SWAP-C, an acronym that denotes the size, weight, energy and value requirements for programs in a lot of functions, reminiscent of phased-array radar systems, unmanned motors, electronic warfare platforms and satellites.

The SHIP program is geared for packaging, despite the fact Qorvo will provide a one-cease store. it'll continue to supply foundry and packaging capabilities for mil/aero purchasers. “We’re modeling it after their foundry mannequin. We’re using the equal sort of open entry category of mannequin. And this might be a carrier. You could design in their foundry. and then you may say, ‘are you able to take those parts and then put them right into a equipment?’ So here's an addition or expansion of their present skill,” White spoke of.

in the meantime, mil/aero involves customized work. each and every client may additionally have diverse packaging requirements with a number of challenges.

Take RF, for example. “one of the vital challenges that you've got in the RF group is, when you put a device into a kit, it adjustments the RF efficiency,” White said. “You need to design your chips and your MMICs to fit interior these packages, and to perform as close as you probably can to their original supposed performance.”

With that in mind, constructing a chiplets model around RF is more convenient observed than finished. “(SHIP) is targeted to make use of GaN, GaAs and silicon. they will additionally all be built-in interior of these heterogeneous packages,” White talked about. “The higher in frequency you go, the greater challenging it turns into to do a chiplet-classification design. That’s probably the most areas that we’re exploring as part of SHIP. here is doing what the government would call a chiplet-classification of a design. And that’s not been absolutely described yet.”

ConclusionThere are a whole lot of different markets which are expected to push toward greater heterogeneous integration. Apple’s low-conclusion Mac computers are relocating to an internally developed M1 processor that integrates CPU cores, photos, a laptop learning engine in a “personalized package,” in keeping with the enterprise.

That is just the starting, too. There are new alternatives for packaging in different markets, comparable to 5G, AI, cellular, and a lot of challenges to go along with them. however there looks to be no scarcity of possibility to maintain the trade busy, amid the brand new and huge adjustments taking vicinity available in the market.

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