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Test Number : E20-920
Test Name : Cloud Services Expert test for Cloud Architects
Vendor Name : EMC
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E20-920 test Format | E20-920 Course Contents | E20-920 Course Outline | E20-920 test Syllabus | E20-920 test Objectives

Exam Title : Dell EMC Certified Expert - Cloud Architect - Cloud Services (DECE-CA)
Exam ID : E20-920
Exam Duration : 90 mins
Questions in test : 60
Passing Score : 60%
Official Training : Cloud Services Planning and Design (MR-1CP-ETCSPD)
Exam Center : Pearson VUE
Real Questions : Dell EMC Cloud Services Expert Real Questions
VCE VCE test : Dell EMC E20-920 Certification VCE Practice Test

IT Transformation and Cloud Services 10%
- Describe the nature and features of various industry IT transformation models used to create business value
- Describe features of the ITaaS transformation model and why it is being adopted (drivers, benefits)
- Describe nature of the cloud services and how they tie into the four ITaaS Focus areas (governance, finance, organization, and technology), as well as planning and design considerations for creating an environment for building and delivering cloud services

Technology Planning 30%
- Identify innovative practices, tools, and technologies (e.g., DevOps, Microservices, open source) that influence the creation of cloud native applications and cloud services; Contrast these with traditional application development
- Describe workload considerations, analysis, and right sourcing as well as assessment of current applications profiles and existing services
- Identify backend technology processes and tools that might aid in delivering cloud services as well as the significance, and benefits, of measuring and reporting for cloud services
- Identify characteristics of, and considerations for, orchestration and automation and their important role in moving from traditional IT capabilities to delivering cloud services
- Describe the nature and use of Service Catalogs and Service Templates and the tie-in to Orchestration

Governance Planning, Security, and Trust 18%
- Describe the nature of, and key considerations pertaining to, governance for cloud services
- Describe the nature of, and key considerations pertaining to, risk management for cloud services
- Describe the nature of, and key considerations pertaining to, compliance and auditing for cloud services
- Describe the nature of, and key considerations pertaining to, security and trust with cloud services

Financial Planning 10%
- Describe financial goals and considerations in support of cloud services; understand the terms CAPEX, OPEX, ROI, and Cost to serve
- Describe considerations for service funding as well as details for service costing and pricing
- Describe the nature and use of Chargeback and Showback financial information

Organizational Planning 10%
- Characterize the challenges (e.g., legacy tools, culture, service maturity level) typically faced by organizations that plan to deliver cloud services
- Describe the considerations (e.g., alignment, cross functional teams, DevOps) for organizations that are transitioning to cloud services within an ITaaS model
- Describe the organizational roles, responsibilities, and competencies required for deploying cloud based services; identifying skills and gaps; developing related training

Service Creation and Management 15%
- Describe the strategy and related considerations for overall service design, taking into consideration various deployment models
- Describe key components of service creation, including: template, offering, contract, and orchestration
- Describe key components of service operations and management including: visibility and control, management, reporting and alerting, termination of services

Emerging Trends in Cloud Services 7%
- Identify emerging trends in technology that are reshaping social behaviors, businesses, including a movement towards a more digital world
- Describe emerging transformation of cloud services delivery resulting from converged infrastructure and operations engineering, with emphasis on how IT can deliver business value through the leveraging of modern applications and software defined approaches

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EMC Expert test

height current Mode handle Will not ever Die!?? | E20-920 Test Prep and real questions

Electronicdesign Com Images Spacer

Fig 1. The buck converter schematic suggests the voltage remarks loop and the fast top CMC loop. The present waveform as considered by the shunt is the dominant sign at the ramp of the PWM comparator.

  • Electronicdesign Com Images Spacer

    Fig 2. as the input voltage rises, the slope across the inductor changes on a cycle foundation in the waveforms of the buck converter with peak CMC. here is the very equal slope that the comparator of the PWM sees, so it’s an almost instantaneous feedforward.

  • Electronicdesign Com Images Spacer

    Fig three. With the onset of an overcurrent event in one switch, which you can see how that perturbation explanations an expanding can charge imbalance in the bulk capacitors within the schematic and waveforms of the half bridge converter with top CMC.

  • Electronicdesign Com Images Spacer

    Fig 4. When it involves the PFC circuit with peak CMC and the consequent section shift of the existing waveform, it's the slope that terminates the pulses within the PWM controller. this is able to clearly trigger a mild part shift within the line present waveform with appreciate to the line voltage.

  • As a teenager, I watched Dee Snider of the rock band Twisted Sister combat over the censorship of rock and roll with Tipper Gore and the folks music resource core. Being somewhat concerned for the way forward for rock and roll, I took solace in some words from Brian Johnson of AC/DC: “Rock and roll ain’t noise pollution…. Rock and roll will certainly not die.”

    As parallel to this, with more and more digital controls entering the switched-mode energy-give (SMPS) control market, there are further and further skeptics when it comes to the way forward for height existing-mode manage (CMC). i wonder if height CMC will continue to exist like rock and roll did.

    the place Did height CMC Come From?

    firstly, Cecil Deisch invented peak CMC at Bell Labs/Western electric to balance the flux in the transformer in a push-pull converter and maintain the core from strolling off into saturation from a minor volt*time product change led to by using slightly asymmetric force waveforms and/or load transients.

    The answer was proven by putting a few quick PN junctions in sequence with the drain or collector of a switch on one leg, forcing a substantial volt*time imbalance. top CMC would terminate the pulses on the unburdened leg early, holding the flux balanced and permitting the converter to run and transfer vigor to the load. in advance of this, there become no similar correction mechanism.  

    How Does It Work?

    It’s historic hat for a lot of us, but I haven’t seen a realistic clarification of top CMC for reasonably a while. peak CMC places a fast current loop internal the voltage control loop. This loop senses the inductor existing and uses this tips as the ramp signal to the heartbeat-width modulation (PWM) comparator. This loop can interrupt the drive to the output devices in the propagation lengthen time of the heartbeat-width modulator and driver when a fault is detected. determine 1 depicts height CMC in a buck converter.

    however the real great thing about the topology lies within the switch function of the converter. in view that height CMC uses the output existing because the ramp to the PWM comparator, the output inductor conveniently drops out of the switch feature of the converter at most any situation with output current. This then makes the double pole at the resonant frequency of the output inductor and output capacitor bank appear to be a single pole.

    A single pole operates with less section/time lag, so a converter with peak CMC can have superior transient response than a converter with voltage-mode PWM handle. youngsters, there are places the place this isn’t true, particularly the multiphase processor vigor world, where add-ons to the voltage-mode manage loop turn on all phases when a transient excessive latest load transient is detected. 

    The different expertise of having this quickly interior loop is that of a feedforward. here's no longer completely obvious. accept as true with the output inductor present waveform for a couple of cycles when the road voltage is increasing. in the beginning, the slope of the inductor latest is at some nominal value. however as line increases, the secondary voltage raises. The output hasn’t changed, so the slope of the latest waveform has to get steeper (bear in mind: V = –Ldi/dt). This steeper current waveform will terminate the cycle greater immediately, decreasing the obligation cycle. consequently, it acts as a fast feedforward.

    This can also be considered in determine 2, which shows us the waveforms from the converter and peak CMC handle in figure 1. The slope adjustments instantaneously as the voltage excitation changes—nearly an immediate feedforward in situ. through evaluation, in a voltage-mode controller, they might look ahead to the road transient to raise the output voltage just a little. Then, the voltage-mode controller would fold lower back the responsibility cycle of the PWM output after some PID loop time consistent.

    Caveats Of top CMC

    There are places the place peak CMC gained’t work without extra circuitry. Let’s trust an offline half bridge converter with a gentle overcurrent adventure or asymetry within the secondary (depicted with the extra diodes in figure 3). this will trigger a prime change to turn off early, developing an expanding cost imbalance in the decoupling capacitors that preserve the return voltage at VCC/2.

    This charge imbalance shows up as a voltage change at the midpoint so the midpoint voltage isn't any longer equal to VCC/2. The very subsequent cycle will see a decrease capacitor voltage in its respective loop, so the current will take longer to ramp as much as the shutdown cost on the comparator. The subsequent cycle will see an excellent larger imbalance in the midpoint voltage and carry a tons bigger voltage to the basic. as a result, the heartbeat will terminate lots prior as a result of the higher slope of the current ramp. The subsequent pulse will see an even reduce voltage and take even longer to terminate. You get the thought.

    The can charge imbalance within the capacitors brought about by way of the primary asymmetrical interrupt caused by top CMC builds on a cycle via cycle basis. The end result of here's a midpoint voltage it is shifted to both VCC or ground and might be a saturated transformer, although the peak CMC mechanism tried to appropriate the situation. There are how one can get round this, equivalent to setting up a pulse-width handle circuit to retain the can charge (and VCC/2) stability within the decoupling caps.  

    In a height CMC energy component correction (PFC) circuit, there is a little extreme distortion within the line current waveform as a result of a moderate offset brought about by using the height CMC comparator. This needs a little clarification. at the minima of the rectified ac line enter, the duty cycle of the PFC is at or near its highest. The on time is very massive, and the off time is terribly small. This occurs on both sides of a half wave of the ac sine.

    This serves to retard the latest waveform a little bit with respect to the voltage waveform. The power ingredient can’t be top-quality, however it can nevertheless be reasonably good. this is considered as a slight phase extend, with a worst case time value of 1/fsw. If they rationalize this towards the length of an ac line cycle, it is a extremely minimal part lengthen, lower than 0.12% or 0.43° for a one hundred-kHz PFC stage and 60-Hz line frequency. In most instances this isn’t an issue, but useful of mentioning. standard CMC resolves this issue (Fig. 4).    

    within the academic world, they are taught that slope compensation is required for obligation cycles beyond 50%. this is easily proven. With a buck converter as the automobile, they are able to set up a converter the place the enter is 10 V, the output is 7.5 V, and the load existing is tremendous with only the output current because the ramp signal on the comparator. below these situations, the inductor latest is clearly in continual conduction mode.

    Let’s then have a load transient that reasons the top CMC loop to interrupt the force to the excessive-facet swap a bit of early. be aware that there's a very brief time for the inductor latest to decay and the flux in the inductor core to reset itself. the weight voltage determines the falling slope of the inductor. as long as the weight isn’t shorted, the current within the output inductor will take a long time to ramp down to the decrease threshold price on the PWM comparator. 

    When the clock initiates the next cycle, the switch in no way activates, because the present continues to be too high (or it turns on very briefly on the minimal responsibility cycle of the controller). If the present is basically high, the subsequent cycle may additionally see the same conditions and remain with ease off. This situation will make the converter oscillate at some subharmonic of the switching frequency of the clock of the PWM.

    Slope compensation cures this by means of introducing a means to bring the ramp right down to zero during the short deadtime. The ramp of the interior clock sign is summed with the sensed existing waveform. there'll still be very short pulses for overcurrent situations, but through summing the clock signal in with the existing signal they now have created a way to resolve this subharmonic oscillation. In purposes, I’ve discovered it more straightforward to use slope compensation for most any responsibility cycle in height CMC operation easily as a result of noise on the existing waveform and the high bandwidth of the comparator that sees this signal. 

    “My DSP engineers will emulate that essential stuff in two hours!”

    A DSP knowledgeable as soon as told me that top CMC changed into convenient to emulate and that he’d have a working answer that behaved similar to top CMC in “two hours.” 5 years later, he had something that remotely resembled peak CMC working at a distance at a change show. It couldn’t address a brief circuit and had no feedforward. He also outlined that analog manage was fully lifeless and now not essential. however I didn’t have many years to attend and spot how he’d obsolete analog control with a different “two-hour repair.”

    hot air however, there have been some marvelous breakthroughs within the digital control of power supplies. The multiphase-processor vigour arena continues to peer extraordinary elements smartly beyond margining a trim digital-to-analog converter (DAC) with VID codes.

    What Does It charge?

    In most designs, it receives all the way down to dollars and cents. If I open the Digi-Key catalog and evaluate the UC3842 types towards small microprocessors at similar volumes, the height CMC IC comes in more affordable. yes, the microprocessor or DSP can add in more aspects. Slope compensation and poles, zeros, and good points within the control loop may also be parametrics in a GUI. Margining can even be programmed, as can min and max duty cycles, fitness monitoring, reporting, and so forth. These are splendid features that many excessive-conclusion vigor-provide designers are for the reason that.

    but when it gets down to pinching pennies, possibly in a silver field, a lights ballast, a bias provide, or a cost-delicate charger, top CMC hold its foothold. in terms of silicon real estate, a high-speed comparator, error amp, and bandgap require an awful lot much less space than comparable processing and logic cells. Silicon true estate has been proven to correlate well to cost, so the smaller top CMC manage die area is more affordable.

    The way forward for top CMC

    If I placed on my advertising cap, I’ve viewed the UC3842 controller, the groundwork of most any peak CMC design, cloned by using extra companies than an LM2902 quad op amp or the TL431 reference. I’ve considered advancements to the IC that took it right into a lower bias present biCMOS design procedure. each different SMPS that I’ve benchmarked had a UC3842 in it somewhere. peak CMC is far from long gone.

    The future of top CMC may be enjoyable. they can possible see an ingress of digital elements to the peak CMC structure and true mixed-mode IC design elements. The digital designers will recognize that a quick comparator is simpler if left as a quick comparator and never emulated. The analog designers will take talents of trim DACs, reporting, and maybe a GUI to program poles and zeros within the handle loop. The effect may be a fine controller with lots of cool features once everyone’s pride heals up and the advertising entropy subsides.


    confidently I’ve offered an inexpensive knowing of height CMC and it’s origins, makes use of, and caveats. It’s a longtime favorite handle system of mine, and i’ve found that the talents is scattered at top of the line. Having spent a lot of time designing SMPSs, I agree with top CMC will survive simply as hearty as the wailings of Brian Johnson and his predecessor Bon Scott, since it too “makes decent respectable feel” even if in terms of the efficiency or can charge. The leading controller ICs will eventually incorporate digital aspects and maybe a GUI, however there’s no primary microcode exchange for peak CMC.

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